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spintronics

Role Overview

Responsible for implementing and validating Design-for-Test (DFT) methodologies to ensure high test coverage and silicon quality.

Key Responsibilities

  • Define and implement DFT architecture for SoC/IP

  • Scan insertion, stitching, and compression

  • Implement Boundary Scan (IEEE 1149.1/1149.6) and IJTAG (1687)

  • Memory BIST, repair, and diagnosis

  • Test point insertion and coverage improvement

  • ATPG pattern generation, simulation, and debug

  • Work with design/PD teams for DFT closure

Required Skills

  • Tools: Synopsys DFT Compiler, Tessent, Modus

  • Strong knowledge of scan, ATPG, BIST

  • Experience in gate-level simulation and debug

  • Understanding of timing, power, and physical constraints

spintronicsAI

DFT Engineer

Apply For this Job

(4–6 Years)

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