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spintronics ai

  1. Design Verification Engineer

  • Synthesis / RTL-to-Gates Engineer

(4–6 Years)

(4–6 Years)

Role Overviews

  1. Ensure functional correctness of RTL through advanced verification methodologies.

  • Convert RTL into optimized gate-level netlist meeting timing, area, and power targets.

  1. Key Responsibilities

  • Develop UVM-based testbenches

  • Write test cases and sequences

  • Functional coverage and closure

  • Debug RTL issues and regressions

  • Assertions and protocol verification

  1. Required Skills

  • SystemVerilog, UVM

  • Tools: VCS, Questa, Xcelium

  • Strong debugging and scripting skills

  • Experience in protocols (PCIe, AXI, etc.) preferred

  • Key Responsibilities

  • RTL synthesis and optimization

  • Constraint development (SDC)

  • Timing analysis and closure support

  • LEC (RTL vs Netlist equivalence)

  • Work with PD for timing convergence

  • Required Skills

  • Tools: Design Compiler / Genus

  • Strong understanding of STA basics

  • Experience in low-power design (UPF)

  • Scripting (Tcl, Python)

spintronicsAI

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